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1 x9258 low noise/low power/ 2-wire bus/256 taps quad digital controlled potentiometers (xdcp?) the x9258 integrates 4 digita lly controlled potentiometers (xdcp?) on a monolithic cmos integrated circuit. the digitally controlled potentio meter is implemented using 255 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through t he 2-wire bus interface. each potentiometer has associated with it a volatile wiper counter register (wcr) and 4 non-volatile data registers (dr0:dr3) that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. power-up recalls the contents of dr0 to the wcr. the xdcp? can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. features ? four potentiometers in one package ? 256 resistor taps/potentiometer................. 0.4% resolution ? 2-wire serial interface ? wiper resistance, 40 typical @ v+ = 5v, v- = -5v ? four nonvolatile data registers for each potentiometer ? nonvolatile storage of wiper position ? standby current <5a max (total package) ? power supplies -v cc = 2.7v to 5.5v - v+ = 2.7v to 5.5v - v- = -2.7v to -5.5v ?100k , 50k total potentiometer resistance ? high reliability - endurance: 100,000 data changes per bit per register - register data retention . . . . . . . . . . . . . . . . . . 100 years ? 24 ld soic, 24 ld tssop ? dual supply version of x9259 ? pb-free available (rohs compliant) block diagram interface and control circuitry scl sda a0 a1 a2 a3 r 0 r 1 r 2 r 3 wiper counter register (wcr) resistor array pot 1 v h1 /r h1 v l1 /r l1 r 0 r 1 r 2 r 3 wiper counter register (wcr) v h0 /r h0 v l0 /r l0 data 8 v w0 /r w0 v w1 /r w1 r 0 r 1 r 2 r 3 resistor array v h2 /r h2 v l2 /r l2 v w2 /r w2 r 0 r 1 r 2 r 3 resistor array v h3 /r h3 v l3 /r l3 v w3 /r w3 wiper counter register (wcr) wiper counter register (wcr) pot 3 pot 2 wp pot 0 v cc v ss v+ v- caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2005, 2006, 2011. all rights reserved xdcp is a trademark of intersil americas inc. intersil (and de sign) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. data sheet fn8168.5 april 14, 2011
2 fn8168.5 april 14, 2011 ordering information part number part marking v cc limits (v) potentiometer organization (k ) temperature range (c) package pkg. dwg. # x9258us24* , ** x9258us 5 10 100 0 to +70 24 ld soic (300 mil) m24.3 x9258us24z* , ** (note) x9258us z 0 to +70 24 ld soic (300 mil) (pb-free) m24.3 x9258us24i* , ** x9258us i -40 to +85 24 ld soic (300 mil) m24.3 x9258us24iz* , ** (note) x9258us zi -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9258uv24 x9258uv 50 0 to +70 24 ld tssop (4.4mm) mdp0044 x9258uv24i x9258uv i -40 to +85 24 ld tssop (4.4mm) mdp0044 x9258uv24iz (note) x9258uv zi -40 to +85 24 ld tssop (4.4mm) (pb-free) mdp0044 x9258ts24* x9258ts 100 0 to +70 24 ld soic (300 mil) m24.3 x9258ts24z (note) x9258ts z 0 to +70 24 ld soic (300 mil) (pb-free) m24.3 x9258ts24i* x9258ts i -40 to +85 24 ld soic (300 mil) m24.3 x9258ts24iz* (note) x9258ts zi -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9258tv24 x9258tv 0 to +70 24 ld tssop (4.4mm) mdp0044 x9258tv24i x9258tv i -40 to +85 24 ld tssop (4.4mm) mdp0044 x9258us24-2.7* x9258us f 2.7 to 5.5 0 to +70 24 ld soic (300 mil) m24.3 x9258us24z-2.7* (note) x9258us zf 0 to +70 24 ld soic (300 mil) (pb-free) m24.3 x9258us24i-2.7* x9258us g -40 to +85 24 ld soic (300 mil) m24.3 x9258us24iz-2.7* , ** (note) x9258us zg -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9258uv24-2.7* x9258uv f 50 0 to +70 24 ld tssop (4.4mm) mdp0044 x9258uv24i-2.7 x9258uv g -40 to +85 24 ld tssop (4.4mm) mdp0044 x9258uv24iz-2.7 (note) x9258uv zg -40 to +85 24 ld tssop (4.4mm) (pb-free) mdp0044 x9258ts24-2.7* x9258ts f 100 0 to +70 24 ld soic (300 mil) m24.3 x9258ts24z-2.7* (note) x9258ts zf 0 to +70 24 ld soic (300 mil) (pb-free) m24.3 x9258ts24i-2.7* x9258ts g -40 to +85 24 ld soic (300 mil) m24.3 x9258ts24iz-2.7* (note) x9258ts zg -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9258tv24-2.7 x9258tv f 0 to +70 24 ld tssop (4.4mm) mdp0044 x9258tv24i-2.7 x9258tv g -40 to +85 24 ld tssop (4.4mm) mdp0044 x9258tv24iz-2.7 (note) x9258tv zg -40 to +85 24 ld tssop (4.4mm) (pb-free) mdp0044 x9258tv24z-2.7 (note) x9258tv zf 0 to +70 24 ld tssop (4.4mm) (pb-free) mdp0044 *add ?t1? suffix for tape and reel. please refer to tb347 for details on reel specifications. **add ?t2? suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free plastic packaged pr oducts employ special pb-free material sets; molding compounds/die attach materi als and 100% matte tin plate plus anneal - e3 terminati on finish, which is rohs compliant and compatible with both snpb and pb-free solderin g operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std- 020. x9258
3 fn8168.5 april 14, 2011 pinout x9258 (24 ld soic, tssop) top view pin descriptions host interface pins serial clock (scl) the scl input is used to clock data into and out of the x9258. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire- ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to ?guidelines for calculating typical values of bus pull-up resistors? on page 10. device address (a 0 - a 3 ) the address inputs are used to set the least significant 4 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9258. a maximum of 16 devices may occupy the 2-wire serial bus. potentiometer pins v h /r h (v h0 /r h0 - v h3 /r h3 ), v l /r l (v l0 /r l0 - v l3 /r l3 ) the v h /r h and v l /r l inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. v w /r w (v w0 /r w0 - v w3 /r w3 ) the wiper outputs are equivalent to the wiper output of a mechanical potentiometer. hardware write protect input (wp) the wp pin when low prevents nonvolatile writes to the data registers. analog supplies v+, v- the analog supplies v+, v- are the supply voltages for the dcp analog section. pin names principles of operation the x9258 is a highly integrat ed microcircuit incorporating four resistor arrays and thei r associated registers and counters and the serial interface logic providing direct communication between the host and the dcp potentiometers. serial interface (2-wire) the x9258 supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always nc a0 v w3 /r w3 v+ v cc v l0 /r l0 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 a3 scl v l2 /r l2 v h2 /r h2 v w2 /r w2 v? v ss v w1 /r w1 v h1 /r h1 v l1 /r l1 x9258 v h3 /r h3 14 13 11 12 v l3 /r l3 v h0 /r h0 v w0 /r w0 a2 a1 sda wp symbol description scl serial clock sda serial data a0 thru a3 device address v h0 /r h0 thru v h3 /r h3 , v l0 /r l0 thru v l3 /r l3 potentiometer pins (terminal equivalent) v w0 /r w0 thru v w3 /r w3 potentiometers pins (wiper equivalent) wp hardware write protection v+, v- analog supplies v cc system supply voltage v ss system ground nc no connection (allowed) x9258
4 fn8168.5 april 14, 2011 initiate data transfers and provide the clock for both transmit and receive operations. therefore, the x9258 will be considered a slave device in all applications. clock and data conventions data states on the sda line can change only during scl low periods (t low ). sda state changes during scl high are reserved for indicating start and stop conditions. start condition all commands to the x9258 are preceded by the start condition, which is a high to low transition of sda while scl is high (t high ). the x9258 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition is met. stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. acknowledge acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. the transmitting device, either t he master or the slave, will release the sda bus after transmitting 8 bits. the master generates a ninth clock cycle and during this period the receiver pulls the sda line lo w to acknowledge that it successfully received the 8 bits of data. the x9258 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. if the command is followed by a data byte, the x9258 will respond with a final acknowledge. array description the x9258 is comprised of four resistor arra ys. each array contains 255 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (v h /r h and v l /r l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (v w ) output. within each individual array only one switch may be turned on at a time. these s witches are controlled by the wiper counter register (wcr). the 8 bits of the wcr are decoded to select, and enable, one of 256 switches. the wcr may be written direct ly, or it can be changed by transferring the contents of on e of four associated data registers into the wcr. thes e data registers and the wcr can be read and written by the host system. device addressing following a start condition t he master must output the address of the slave it is a ccessing. the most significant 4 bits of the slave address are the device type identifier (refer to figure 1). for the x9258 this is fixed as 0101[b]. the next 4 bits of the slave address are the device address. the physical device address is de fined by the state of the a0 thru a3 inputs. the x9258 compares the serial data stream with the address input state; a successful compare of all 4 address bits is required for the x9258 to respond with an acknowledge. the a 0 thru a 3 inputs can be actively driven by cmos input signals or tied to v cc or v ss . acknowledge polling the disabling of the inputs (during the internal nonvolatile write operation), can be used to take advantage of the typical 5ms nonvolatile writ e cycle time. on ce the stop condition is issued to indicate the end of the nonvolatile write command, the x9258 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by t he device slave address. if the x9258 is still busy with the write operation, no ack will be returned. if the x9258 has completed the write operation an ack will be returned and the master can then proceed with the next operation. 1 00 a3 a2 a1 a0 device type identifier device address 1 figure 1. slave address x9258
5 fn8168.5 april 14, 2011 ack polling sequence instruction structure the next byte sent to the x925 8 contains the instruction and register pointer information. the four most significant bits are the instruction. the next four bits point to one of the two potentiometers and when applicable they point to one of four associated registers. the format is shown in figure 2. . the four high order bits define the instruction. the next 2 bits (r1 and r0) select one of the four registers that is to be acted upon when a register ori ented instruction is issued. the last bits (p1, p0) select which one of the four potentiometers is to be affected by the instruction. four of the nine instructions end with the transmission of the instruction byte. the basic sequence is illustrated in figure 3. these two-byte instructions exchange data between the wiper counter register and one of the data registers. a transfer from a data register to a wiper counter register is essentially a write to a static ram. the response of the wiper to this action will be delayed t wrl . a transfer from the wiper counter register (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four pot entiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between all of the potentiometers and one of their associated registers. four instructions require a three-byte sequence to complete. these instructions transfer data between the host and the x9258; either between the host and one of the data registers or directly between the host and the wiper counter register. these instructions are: read wiper counter register (read the current wiper position of the selected potentiometer), write wiper counter register (change current wiper position of the selected potentiometer), read data register (read the contents of the selected nonvol atile register) and write data register (write a new value to the selected data register). the sequence of operations is shown in figure 4. nonvolatile write command completed enter ack polling issue start issue slave address ack returned? further operation? issue instruction issue stop no yes yes proceed issue stop no proceed figure 2. instruction byte format i1 i2 i3 i0 r1 r0 p1 p0 wiper counter register select instructions register select s t a r t 0101a3a2a1a0 a c k i3 i2 i1 i0 r1 r0 p1 p0 a c k scl sda s t o p figure 3. two-byte instruction sequence x9258
6 fn8168.5 april 14, 2011 the increment/decrement command is different from the other commands. once the command is issued and the x9258 has responded with an a cknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. for each scl clock pulse (t high ) while sda is high, the selected wiper will move one resistor segment towards the v h terminal. similarly, for each scl clock pulse while sda is low, the selected wiper will move one resistor segment towards the v l /r l terminal. a detailed illustration of the sequence and timing for this operation are shown in figures 5 and 6 respectively. table 1. instruction set instruction instruction set operation i 3 i 2 i 1 i 0 r 1 r 0 p 1 p 0 read wiper counter register 1 0 0 1 0 0 1/0 1/0 read the contents of the wiper counter register pointed to by p 1 - p 0 write wiper counter register 1 0 1 0 0 0 1/0 1/0 write new value to the wiper counter register pointed to by p 1 - p 0 read data register 1 0 1 1 1/0 1/0 1/0 1/0 read the contents of the data register pointed to by p 1 - p 0 and r 1 - r 0 write data register 1 1 0 0 1/0 1/0 1/0 1/0 write new value to the data register pointed to by p 1 - p 0 and r 1 - r 0 xfr data register to wiper counter register 1 1 0 1 1/0 1/0 1/0 1/0 transfer the contents of the data register pointed to by p 1 -p 0 and r 1 - r 0 to its associated wiper counter register xfr wiper counter register to data register 1 1 1 0 1/0 1/0 1/0 1/0 transfer the contents of the wiper counter register pointed to by p 1 - p 0 to the data register pointed to by r 1 - r 0 global xfr data registers to wiper counter registers 0 0 0 1 1/0 1/0 0 0 transfer the contents of the data registers pointed to by r 1 - r 0 of all four potentiometers to their respective wiper counter registers global xfr wiper counter registers to data register 1 0 0 0 1/0 1/0 0 0 transfer the contents of both wiper counter registers to their respective data registers pointed to by r 1 - r 0 of all four potentiometers increment/decrement wiper counter register 0 0 1 0 0 0 1/0 1/0 enable increment/decrement of the control latch pointed to by p 1 - p 0 note: 1. 1/0 = data is one or zero. x9258
7 fn8168.5 april 14, 2011 i f i s t a r t 0 1 0 1 a3 a2 a1 a0 a c k i3 i2 i1 i0 r1 r0 p1 p0 a c k scl sda s t o p a c k d7 d6 d5 d4 d3 d2 d1 d0 figure 4. three-byte instruction sequence figure 5. increment/decrement instruction sequence s t a r t 0 1 0 1 a3 a2 a1 a0 a c k i3 i2 i1 i0 r0 p1 p0 a c k scl sda s t o p i n c 1 i n c 2 i n c n d e c 1 d e c n r1 figure 6. increment/decrement timing limits scl sd a v w /r w inc/dec cmd issued voltage out t wrid scl from data output 1 89 start acknowledge master from transmitter data output from receiver figure 7. acknowledge response from receiver x9258
8 fn8168.5 april 14, 2011 all dcp potentiometers share the serial interface and share a common architecture. each potentiometer has a wiper counter register and four data registers. a detailed discussion of the register organization and array operation follows. wiper counter register the x9258 contains four wipe r counter registers, one for each dcp potentiometer. the wiper counter register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. the contents of the wcr can be altered in four ways: 1. written directly by the host via the write wiper counter register instruction (serial load) 2. written indirectly by transferring the contents of one of four associated data registers via the xfr data register instruction (parallel load) 3. can be modified one step at a time by the increment/decrement instruction. 4. loaded with the contents of its data register zero (r0) upon power-up. the wcr is a volatile register; that is, its contents are lost when the x9258 is powered-down. although the register is automatically loaded with the va lue in r0 upon power-up, it should be noted this may be different from the value present at power-down. data registers each potentiometer has four nonvolatile data registers. these can be read or written directly by the host and data can be transferred between any of the four data registers and the wcr. it should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not r equire storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. register descriptions data registers, (8-bit), nonvolatile four 8-bit data registers for each dcp (sixteen 8-bit registers in total). {d7~d0}: these bits are for gener al purpose not volatile data storage or for storage of up to four different wiper values. the contents of data register 0 are automatically moved to the wiper counter register on power-up. figure 8. detailed potentiometer block diagram detailed operation serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input wiper counter register inc/dec logic up/dn clk modified scl up/dn v h /r h v l /r l v w /r w if wcr = 00[h] then v w /r w = v l /r l if wcr = ff[h] then v w /r w = v h /r h 8 8 (wcr) counter decoder wp7 wp6 wp5 wp4 wp3 wp2 wp1 wp0 nv nv nv nv nv nv nv nv (msb) (lsb) x9258
9 fn8168.5 april 14, 2011 wiper counter register, (8-bit), volatile one 8-bit wiper counter register for each dcp (four 8-bit registers in total.) {d7~d0}: these bits specify the wiper position of the respective dcp. the wiper counter register is loaded on power-up by the value in data register 0. the contents of the wcr can be loaded from any of the other data register or directly. the contents of the wcr can be saved in a dr. instruction format notes: 2. ?mack?/?sack?: stands for the acknowledge sent by the master/slave. 3. ?a3 ~ a0?: stands for the device addresses sent by the master. 4. ?x?: indicates that it is a ?0? fo r testing purpose but physically it is a ?don?t care? condition. 5. ?i?: stands for the increment operation, sda held high during active scl phase (high). 6. ?d?: stands for the decrement operation, sda held low during active scl phase (high). read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) write data register (wr) wp7 wp6 wp5 wp4 wp3 wp2 wp1 wp0 v vvvvvv v (msb) (lsb) s t a r t device type identifier device addresses s a c k instruction opcode wcr addresses s a c k wiper position (sent by slave on sda) m a c k s t o p 0101a3a2a1a0 100100p1p0 wp7wp6wp5wp4wp3wp2wp1wp0 s t a r t device type identifier device addresses s a c k instruction opcode wcr addresses s a c k data byte (sent by master on sda) s a c k s t o p 0101a3a2a1a0 101000p1p0 wp7wp6wp5wp4wp3wp2wp1wp0 s t a r t device type identifier device addresses s a c k instruction opcode dr and wcr addresses s a c k data byte (sent by slave on sda) m a c k s t o p 0101a3a2a1a0 1 0 1 1r1r0p1p0 wp7wp6wp5wp4wp3wp2wp1wp0 s t a r t device type identifier device addresses s a c k instruction opcode dr and wcr addresses s a c k data byte (sent by master on sda) s a c k s t o p high-voltage write cycle 0101a 3 a 2 a 1 a 0 1 1 0 0 r1 r0 p1 p0 wp7 wp6 wp5 wp4 wp3 wp2 wp1 wp0 x9258
10 fn8168.5 april 14, 2011 xfr data register (dr) to wiper counter register (wcr) xfr wiper counter register (w cr) to data register (dr) increment/decrement wiper counter register (wcr) global xfr data register (dr) to wiper counter register (wcr) global xfr wiper counter register (wcr) to data register (dr) symbol table guidelines for calculating typical values of bus pull-up resistors s t a r t device type identifier device addresses s a c k instruction opcode dr and wcr addresses s a c k s t o p 0101a3a2a1a0 1101r1r0p1p0 s t a r t device type identifier device addresses s a c k instruction opcode dr and wcr addresses s a c k s t o p high-voltage write cycle 0 1 0 1 a3 a2 a1 a0 1 1 1 0 r1 r0 p1 p0 s t a r t device type identifier device addresses s a c k instruction opcode wcr addresses s a c k increment/decrement (sent by master on sda) s t o p 0 1 0 1 a3 a2 a1 a0 0 0 1 0 0 0 p1 p0 i/d i/d . . . . i/d i/d s t a r t device type identifier device addresses s a c k instruction opcode dr addresses s a c k s t o p 0 1 0 1 a3 a2 a1 a0 0 0 0 1 r1 r0 0 0 s t a r t device type identifier device addresses s a c k instruction opcode dr addresses s a c k s t o p high-voltage write cycle 0101a3a2a1a0 1 0 0 0r1r000 waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance (k) bus capacitance (pf) minimum resistance maximum resistance r max = r min = iol min v cc max =1.8k c bus t r x9258
11 fn8168.5 april 14, 2011 absolute maximum rati ngs thermal information voltage on sda, scl or any address input with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v voltage on v+ (referenced to v ss ) . . . . . . . . . . . . . . . . . . . . . . .10v voltage on v- (referenced to v ss ) . . . . . . . . . . . . . . . . . . . . . . . -10v (v+) - (v-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12v any v h /r h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v+ any v l /r l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v- i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ma thermal resistance (typical, note 7) ja (c/w) 24 lead soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 24 lead tssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65c to +135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65 c to +150 c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage range (typical) x9258. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v 10% x9258-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 7. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 8. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. analog specifications over recommended operating conditi ons, unless otherwise specified. symbol parameter test conditions min (note 8) typ max (note 8) unit end-to-end resistance tolerance 20 % power rating +25c, each potentiometer 50 mw i w wiper current wiper current = 1ma 7.5 ma r w wiper resistance i w = 1ma @ v+ = 3v, v- = -3v 150 250 r w wiper resistance i w = 1ma @ v+ = 5v, v- = -5v 40 100 v+ voltage on v+ pin x9258 +4.5 +5.5 v x9258-2.7 +2.7 +5.5 v v- voltage on v- pin x9258 -5.5 -4.5 v x9258 -2.7 -5.5 -2.7 v v term voltage on any v h /r h or v l /r l pin v- v+ v noise ref: 1khz -120 dbv resolution (note 12) 0.6 % absolute linearity (note 9) v w(n)(actual) - v w(n)(expected) 1 mi (note 11) relative linearity (note 10) v w(n + 1) - [v w(n) + mi ]0.6mi (note 11) temperature coefficient of r total 300 ppm/ c ratiometric temperature coefficient 20 ppm/c c h /c l /c w potentiometer capacitance see ?test circuit #3 spice macro model? on page 14 10/10/25 pf x9258
12 fn8168.5 april 14, 2011 dc operating characteristics over recommended operating conditi ons, unless otherwise specified. symbol parameter test conditions min (note 8) typ max (note 8) unit i cc1 v cc supply current (nonvolatile write) f scl = 400khz, sda = open, other inputs = v ss 1ma i cc2 v cc supply current (move wiper, write, read) f scl = 400khz, sda = open, other inputs = v ss 100 a i sb v cc current (standby) scl = sda = v cc , addr. = v ss 5a i li input leakage current v in = v ss to v cc 10 a i lo output leakage current v out = v ss to v cc 10 a v ih input high voltage v cc x 0.7 v cc + 0.1 v v il input low voltage -0.5 v cc x 0.3 v v ol output low voltage i ol = 3ma 0.4 v notes: 9. absolute linearity is utilized to determine actual wiper volt age versus expected voltage as determined by wiper position when used as a potentiometer. 10. relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. 11. mi = r t o t /255 or (v h /r h ?v l /r l )/255, single potentiometer. 12. max = all four arrays cascaded together ; typical = individual array resolutions. endurance and data retention parameter min (note 8) unit minimum endurance 100,000 data changes per bit per register data retention 100 years capacitance symbol parameter test conditions max (note 8) unit c i/o (note 13) input/output capacitance (sda) v i/o = 0v 8 pf c in (note 13) input capacitance (a0, a1, a2, a3, and scl) v in = 0v 6 pf power-up timing symbol parameter min (note 8) max (note 8) unit t pur (note 14) power-up to initiation of read operation 1 ms t puw (note 14) power-up to initiation of write operation 5 ms t r v cc (note 15) v cc power-up ramp 0.2 50 v/ms notes: 13. this parameter is periodically sampled and not 100% tested. 14. t pur and t puw are the delays required from the time the third (last) power supply (v cc , v+ or v-) is stable until t he specific instruction can be issued. these parameters are periodically sampled and not 100% tested. 15. sample tested only. x9258
13 fn8168.5 april 14, 2011 power-up and power-down requirement the are no restrictions on the s equencing of the bias supplies v cc , v+, and v- provided that all three supplies reach their final values within 1ms of each other. at all times, the voltages on the potentiometer pins must be less than v+ and more than v-. the recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their final value. the v cc ramp rate specification is always in effect. equivalent ac load circuit ac test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 5v 1533 100pf sda output 2.7v 100pf x9258
14 fn8168.5 april 14, 2011 test circuit #3 spice macro model 10pf r h r total c h 25pf c w c l 10pf r w r l macro model ac timing over recommended operating conditi ons, unless otherwise specified. symbol parameter min (note 8) max (note 8) unit f scl clock frequency 400 khz t cyc clock cycle time 2500 ns t high clock high time 600 ns t low clock low time 1300 ns t su:sta start setup time 600 ns t hd:sta start hold time 600 ns t su:sto stop setup time 600 ns t su:dat sda data input setup time 100 ns t hd:dat sda data input hold time 30 ns t r scl and sda rise time (note 16) 300 ns t f scl and sda fall time (note 16) 300 ns t aa scl low to sda data output valid time 900 ns t dh sda data output hold time 50 ns t i noise suppression time constant at scl and sda inputs 50 ns t buf bus free time (prior to any transmission) 1300 ns t su:wpa wp , a0, a1, a2 and a3 setup time 0 ns t hd:wpa wp , a0, a1, a2 and a3 hold time 0 ns note: 16. a device must internally provide a hold time of at least 300ns for the sda si gnal in order to bridge the undefined region of the falling edge of scl. x9258
15 fn8168.5 april 14, 2011 timing diagrams 2-wire interface start and stop timing input timing output timing high-voltage write cycle timing symbol parameter typ max (note 8) unit t wr high-voltage write cycle time (store instructions) 5 10 ms dcp timing symbol parameter min (note 8) max (note 7) unit t wrpo wiper response time after the third (last) power supply is stable 10 s t wrl wiper response time after instruction issued (all load instructions) 10 s t wrid wiper response time from an active scl/sc k edge (increment/decrement instruction) 10 s t su:sta t hd:sta t su:sto scl sda t r (start) (stop) t f t r t f scl sda t high t low t cyc t hd:dat t su:dat t buf scl sda t dh t aa x9258
16 fn8168.5 april 14, 2011 dcp timing (for all load instructions) dcp timing (for increment/decrement instruction) write protect and device address pins timing scl sda vwx (stop) lsb t wrl scl sda vwx t wrid wiper register address increment /decrement incre ment/decrement sda scl ... ... ... wp a0, a1 a2, a3 t su:wpa t hd:wpa (start) (stop) (any instruction) x9258
17 fn8168.5 april 14, 2011 x9258 applications information basic configurations of electronic potentiometers figure 9. three terminal potentiometer; variable voltage divider figure 10. two-terminal variable resistor; variable current v r v w /r w +v r i application circuits figure 11. non-inverting amplifier figure 12. voltage regulator figure 13. offset voltage adjustment figure 14. comparator with hysteresis + ? v s v o r 2 r 1 v o = (1+ r 2 /r 1 ) v s r 1 r 2 i adj v o (reg) = 1.25v (1+ r 2 /r 1 )+ i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 100k 10k 10k 10k -12v +12v tl072 v ul = {r 1 /(r 1 +r 2 )} v o (max) v ll = {r 1 /(r 1 +r 2 )} v o (min ) + ? v s v o r 2 r 1 } }
18 fn8168.5 april 14, 2011 figure 15. attenuator figure 16. filter figure 17. inverting amplifier figure 18. equivalent l-r circuit figure 19. function generator application circuits (continued) + ? v s v o r 3 r 1 v o = g v s -1/2 g +1/2 r 2 r 4 all r s = 10k g o = 1 + r 2 /r 1 fc = 1/(2 rc) + ? v s r 2 r 1 r c v o + ? v s v o r 2 r 1 } } v o = g v s g = - r 2 /r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c x9258
19 fn8168.5 april 14, 2011 x9258 thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol millimeters tolerance 14 ld 16 ld 20 ld 24 ld 28 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. f 2/07 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8168.5 april 14, 2011 x9258 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m m24.3 (jedec ms-013-ad issue c) 24 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.020 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.5985 0.6141 15.20 15.60 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n24 247 0 8 0 8 - rev. 1 4/06

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